The present invention relates to a digital information error checking and correcting apparatus for performing single error correcting (SEC), double error detecting (DED), single byte error detecting (SBED), and odd numbered single byte error correcting (OSBEC).
To improve the reliability of computer memory systems, error-correcting codes (ECC) have been widely used to ensure protection against intermittent, permanent and transitory failures.
SEC-DED codes have been proposed for use in memory systems organized on the basis on one bit per chip.
In this way any failure in a single memory component can influence at most only a single bit of the digital information, hereinafter defined as a codeword.
Standard memory device technology is moving towards ever higher levels of integration and multiple-bit-per-chip memory organizations are becoming common.
In this case a failure in a memory component or chip can generate different types of error:
a failure of a single cell can generate a single error, but an overall chip failure can simultaneously generate an error of several bits, up to a maximum of b, where b is the number of bits simultaneously extracted from the individual memory component. PA1 Document 1:--C. L Chen. My Hsiao: Error Correcting Codes for Semiconductor Memory Application: A state of the Art Review. IBM Journal Of Research & Development, Vol. 28, N. 2, March 1984 PA1 Document 2:--C. L Chen. "Symbol Error-Correcting Codes for Computer Memory Systems" IEEE Transactions on Computers, Vol. 41, pp 252-256. February 1992. PA1 Document 3:--S. Kaneda and E Fujiwara: "Single Byte Error Correcting--Double Byte Error Detecting Codes for Memory Systems" IEEE Transactions on Computers, Vol. C-31 pp 596-602, July 1982.
Therefore, in a memory organization of b bits per chip, a chip failure can generate a "byte error" that is an error configuration consisting of from one up to b error bits, in dependence on the type of failure: cell failure, word line failure, bit line failure, or partial or total chip failure.
The SEC-DED codes are not suitable for memories having b bits per chip since multiple errors are not correctable and the uncorrectable error (UE) rate can become high in the case of chip failure resulting in a high number of multiple byte errors.
Another serious problem is constituted by the loss of data integrity due to the fact that a multiple error could be wrongly corrected by a SEC-DED code.